Our control objective for the jacketed stirred reactor is to maintain reactor exit stream temperature at set point in spite of disturbances caused by a changing cooling liquid temperature entering the vessel jacket. In previous articles, we have established thedesign level of operation for the reactor and explored the performance of a single loop PI controller and a PID with CO Filter controller in meeting our control objective.

We also have proposed a cascade control architecture for the reactor that offers potential for improving disturbance rejection performance. We now apply our proposed architecture following the implementation